sales@ipcb.com
PCB routing must take into account signal integrity, electromagnetic compatibility and manufacturing processes. This article summarises key parameters such as trace width and current matching, high-speed signal classification, layer stacking, impedance matching and ground plane design, providing engineers with a quick reference guide.
Basic Parameter Specifications for PCB Routing
1. Trace Width and Current Matching
Conventional trace widths should be no less than 0.2 mm (8 mil); for high-density, high-precision PCBs, standard trace widths and spacing are typically 0.3 mm (12 mil). Under conditions of 50 μm copper foil thickness, trace widths of 1–1.5 mm (60 mil) can carry a current of 2 A; a trace width of 80 mil is recommended for common ground lines, and PCBs incorporating microprocessors must strictly adhere to this standard.
2. Criteria for High-Speed Signals
The primary criterion is the steepness of the signal edges, rather than the signal frequency. According to the theory in *High-Speed Digital Design*, a signal is considered high-speed if its 10%–90% rise time is less than six times the line delay. Even an 8 kHz square wave signal must be routed according to high-speed transmission line theory, provided the edges are sufficiently steep.
Principles and Advantages of Multi-Layer PCB Stack-Up
1. The power plane should be adjacent to the ground plane and positioned directly beneath it;
2. The signal layer should be adjacent to the mirror image plane to minimise signal interference;
3. The power and ground planes should have the lowest impedance to ensure stable power supply;
4. Intermediate layers should form striplines, whilst the top layer should form microstrip lines to accommodate different transmission requirements;
5. Core signal lines should be adjacent to the ground plane to enhance immunity to interference.
Taking a common 4-layer board (S1 signal layer, S2 signal layer, GND ground layer, POWER power supply layer) as an example, the advantages and disadvantages of the three mainstream stacking schemes are as follows:
Scheme 1 (Optimal): The outer layer is the ground layer, providing good EMI shielding. The distance between the power supply layer and the ground layer is small, and the internal resistance is low. It is not suitable for high-density, high-power PCBs, as it can easily compromise the integrity of the ground layer, leading to a deterioration in the quality of the inner signal layers.
Scheme 2 (Most Common): Simple structure and wide applicability, but high power supply internal resistance. Under high-frequency conditions, spatial radiated interference is strong, requiring the installation of additional shielding plates; not suitable for high-speed digital circuits.
Scheme 3: S1 layer has the best signal quality, followed by the S2 layer; good EMI shielding effect, but power supply impedance is relatively high; suitable for high-power PCB scenarios adjacent to interference sources.
Impedance Matching Rules for High-Speed Circuits
When the load impedance RL equals the transmission line impedance Z₀, there is no reflection at the load; when the source impedance RS equals Z₀, there is no reflection at the source. The standard transmission line impedance is 50Ω, whilst load impedances are typically in the kilo-ohm range, making load-end matching extremely difficult; in contrast, the source output impedance is only around ten ohms, making source-end matching much easier to achieve.
Typical operating conditions: In TTL/CMOS 24mA drive mode, the source output impedance is approximately 13Ω. When paired with a 33Ω source-side matching resistor, the total impedance approximates 50Ω; a slightly underdamped state can optimise signal rise time. In high-speed circuits, critical lines such as clock and control signals must be fitted with source-side matching resistors to eliminate secondary signal reflections.
Key Points for Power and Ground Trace Layout
1. Power Trace Layout
Power traces should be kept as short as possible and routed in straight lines. Tree-like routing is preferred, whilst looped routing is prohibited, to minimise trace impedance and signal interference.
2. Differentiated Design of Ground Loops
The logic behind ground design for digital and analogue circuits is entirely different:
Digital circuits: Closed ground loops are recommended. Digital circuits generate high pulse currents; branched ground traces can easily create potential differences in the order of hundreds of millivolts. Closed loops disperse the current, reducing potential differences to between one-half and one-fifth of the original value, thereby mitigating interference.
Analogue circuits: Ground loops must be broken. Closed loops are prone to introducing power-frequency spatial induction interference, leading to reduced accuracy and the generation of hum. Practical testing of analogue equipment such as precision AD converters and Hi-Fi amplifiers shows that they all employ an open-loop, branched ground design.
General PCB Design Principles and Anti-Interference Measures
1. Layout Principles
Control PCB dimensions appropriately to avoid excessive size leading to increased impedance and costs, or excessive smallness causing poor heat dissipation and signal interference issues. Arrange components according to the functional units of the circuit, adhering to the following core rules:
Shorten the traces of high-frequency components; isolate strong and weak signals, as well as components with high and low potentials, to prevent electromagnetic interference and high-voltage short circuits;
Mount heavy or heat-generating components to the chassis baseplate; position heat-sensitive components away from heat sources; and integrate adjustable components into the overall adjustment mechanism of the unit;
Components near the board edge must be positioned at least 2 mm from the edge; rectangular board dimensions of 3:2 or 4:3 are preferred; and large-sized PCBs require reinforced mechanical structures.
2. Routing Principles
Avoid routing input and output lines in parallel; where necessary, add a ground trace between them to eliminate feedback coupling;
Prioritise widening power and ground traces; for digital circuits, standard trace widths are 0.02–0.3 mm, but widen traces as much as possible where process conditions permit;
Use curved bends for high-frequency traces; avoid right angles and sharp corners; replace large areas of solid copper with a grid pattern to prevent delamination due to heat.
3. Pad Specifications
Pad apertures should be slightly larger than the diameter of the component pins to prevent cold solder joints; for standard pads, the outer diameter D should be ≥(d+1.2) mm, whilst for high-density digital circuits, D may be set to ≥(d+1.0) mm (where d is the pin aperture diameter).
4. Core Interference Suppression Measures
Power Supply Design: Use thicker power supply traces to reduce loop resistance; route power and ground lines in the same direction as data transmission to improve noise immunity;
Ground Design: Separate digital and analogue grounds; use single-point grounding for low-frequency circuits, and short, thick, multi-point grounding with large-area copper grids for high-frequency circuits;
Decoupling Capacitor Configuration: Connect a 10–100 μF electrolytic capacitor to the power supply input; for single chips, use a 0.01 pF ceramic capacitor; where space is limited, 4–8 chips may share a 1–10 pF capacitor; add decoupling capacitors close to memory devices; high-frequency capacitors should be laid out lead-free;
Protection for special components: For spark-generating components such as relays and switches, add RC snubber circuits (R: 1–2 kΩ, C: 2.2–47 μF); ground or connect idle CMOS pins to the power supply to avoid induced interference.
Techniques for Efficient Automatic PCB Routing
1. Determine the board layer structure: In the early design phase, determine the number of routing layers and the stack-up configuration based on the requirements of high-density components such as BGAs. Prioritise a balanced number of layers and uniform copper distribution to avoid subsequent modifications;
2. Set design rules: Classify components by signal priority and specifically define parameters such as trace width, via count, trace parallelism and layer domains to constrain the automatic routing logic;
3. Optimise component placement: Adhere to DFM (Design for Manufacturability) principles, reserving routing paths and via areas to accommodate automatic routing rules;
4. Standardise fan-out design: Reserve vias for SMD component pins, favouring large-sized vias with 50-mil spacing to balance internal routing and in-circuit testing requirements; position capacitor vias close to pins to reduce inductance;
5. Prioritise manual routing of critical signals: Manually route and lock core signals such as clocks, high-frequency signals and control signals to provide a reference for automatic routing and avoid parameter anomalies;
6. Layer-by-layer automatic routing: Complete the routing of general signals layer by layer using layer domains, via and spacing constraints, locking completed lines category by category to reduce mutual interference;
7. Post-routing optimisation and refinement: Manually correct excessively long traces and redundant vias, streamline the routing structure, and optimise the board layout whilst ensuring electrical performance requirements are met.
PCB routing is a systematic engineering process that must address multiple requirements, including signal integrity, electromagnetic compatibility, thermal management and manufacturability. Strict adherence to trace width and current matching guidelines, precise identification of high-speed signal boundaries, appropriate selection of multilayer stack-up configurations, implementation of source-end impedance matching, and differentiation between the ground design logic for digital and analogue circuits can significantly enhance the board’s immunity to interference and its electrical performance. Furthermore, effective use of EDA tools’ automatic routing functions, supplemented by early-stage specification setting and subsequent fine-tuning, can improve design efficiency whilst ensuring the quality of critical signals.